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OpenTimer / OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design vlsi-physical-design sta electronic-design-automation vlsi-circuits static-timing-analysis

Updated Dec 26, 2025
Verilog

clin99 / awesome-eda

Star

open-source parser fpga simulation timer routing verification eda verilog circuit systemverilog gds logic-synthesis lithography placement static-timing-analysis

Updated Jun 26, 2019

OpenTimer / Parser-SPEF

Star

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

eda circuits cpp17 vlsi computer-aided-design vlsi-physical-design sta spef electronic-design-automation vlsi-circuits parasitic static-timing-analysis

Updated Aug 7, 2022
C++

fayizferosh / yosys-tcl-ui-report

Star

5 Day TCL begginer to advanced training workshop by VSD

linux bash open-source csv workshop tcl synthesis yosys shell-scripting vlsi-physical-design hardware-description-language static-timing-analysis tcl-programming tcl-extensions tcl-procedures opentimer eda-tools

Updated Oct 18, 2023
Verilog

Visruat / VSD-TCL

Star

TCL Script automating the frontend of ASIC design

tcl synthesis static-timing-analysis asic-design

Updated Jun 21, 2023
Verilog

ramiomer94 / VLSI-design-projects

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This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools

Updated Jul 12, 2025
Verilog

Circuits-and-Systems-Lab-CASlab / UPSET

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UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

fault-tolerance electronic-design-automation static-timing-analysis fault-analysis single-event-transient

Updated Feb 19, 2026
Verilog

etcimon / GSys-LibreCore

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A source-available, Linux-capable RISC-V application-class super-processor — and the super-intelligence agentic custom-build platform that carries it from core to silicon through bios and pytorch to any GHz desired.

rust cpu eda systemverilog out-of-order risc-v static-timing-analysis

Updated Oct 6, 2026
D

Randy1005 / Ink

Star

Incremental k-Critical Path Generation

graph static-timing-analysis

Updated Jul 4, 2026
C++

MalakSadek / StaticTimingAnalyzer

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A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

python c html json graph-algorithms scl verilog logic-gates verilog-hdl logic-circuit static-timing-analysis

Updated Mar 25, 2021
HTML

kanndil / PathView

Star

An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

eda primetime critical-path-analysis pathview static-timing-analysis opensta schematic-layout electronic-design

Updated Oct 22, 2024
HTML

NaiyarMalik / ttsky-TinyProcessor

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Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects

asic fpga eda fabrication vlsi semiconductor static-timing-analysis openroad gate-level-simulation rtl-design physical-layout-analysis

Updated Oct 7, 2026
Verilog

KarpelesLab / reticle

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A VHDL and Verilog compiler written from scratch in Rust, with no third-party crates: simulation, synthesis, formal verification, FPGA place-and-route, bitstream generation and JTAG programming.