eda-tools

Education kit for teaching VLSI fundamentals through practical microprocessor design using industry EDA tools (educational)

5 Day TCL begginer to advanced training workshop by VSD

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

A web-based tool for parsing and visualizing FPGA. It provides an interactive graph representation of signal propagation, helping engineers and students analyze delays, interconnections, and logic components inside an FPGA.

Browser cockpit & IDE for the LibreLane RTL-to-GDS chip flow — run, verify, and explore silicon flows without living in a terminal.

A collection of Schematics, PCBs and VLSI work on various platforms

Param + EDA — a hierarchical configuration system for EDA tooling: config-folder tree with parent/child scoping, lazy variable substitution, and JSON-backed load/save.

Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.

Design-rule check: a GDS layout + a rule deck in, geometry violations out.

Proteus Design Suite Professional — electronics simulation with SPICE, PCB layout and microcontroller co-simulation.

An integrated educational framework covering semiconductor physics, circuit design, fabrication processes, and testing — from fundamentals to advanced practical applications. （物性・回路・プロセス・設計・テストを貫く一貫教育体系。基礎から応用・実践までを体系的に整理）

AI-powered Verilog/SystemVerilog MCP Server for Claude Code: generate testbenches, lint RTL code, and scaffold UVM verification environments

Design and simulation of 16-bit Ripple Carry and Weinberger Adders using Cadence Virtuoso. Includes full adder modeling, schematic creation, waveform analysis, and detailed delay-power comparison.

Open-source, Python-native EDA toolchain for Low-Power Logic Equivalence Checking (LEC) and IEEE 1801 UPF verification - SAT-based (Yosys) equivalence flow + agentic multi-agent optimization. MIT licensed.

OS-independent CLI tool that checks dependencies for eSim's integrated EDA tools (Ngspice, KiCad, Scilab, Verilator) across Windows, Linux, and macOS. Built as a screening task for the FOSSEE Semester Long Internship.

A local data studio for JSONL/JSON/CSV/TSV/Parquet: scalable previews, image inspection, DuckDB SQL, EDA, and Embedding Atlas.

Layout-vs-schematic: SPICE netlist comparison with clear divergence diagnostics.

A practical day-by-day journey exploring Digital IC Design using Cadence Virtuoso — from schematics to layouts, DRC/LVS checks, parasitic extraction, and timing analysis.

"10-day VSD Physical Verification workshop using the SKY130 open-source PDK and EDA tools".

A mini CPU with control unit, ALU and SRAM implemented in verilog for deploy in a FPGA